On Wed, Jul 7, 2021 at 3:30 AM Arnd Bergmann <arnd@xxxxxxxx> wrote: > > On Tue, Jul 6, 2021 at 6:20 PM Will Deacon <will@xxxxxxxxxx> wrote: > > > > I think the million dollar question is whether the 128-byte cache-lines > > live in a cache above the PoC or not. If it's just a system level cache > > through which all DMA is "coherent", then it doesn't matter. > > On Wed, Jul 7, 2021 at 10:24 AM Yassine Oudjana > <y.oudjana@xxxxxxxxxxxxxx> wrote: > > > > On Wednesday, July 7th, 2021 at 12:33 AM, Arnd Bergmann <arnd@xxxxxxxx> wrote: > > > On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana y.oudjana@xxxxxxxxxxxxxx wrote: > > > > > > > > $ numactl -C 0 line -M 1M > > > > 128 > > > > $ numactl -C 3 line -M 1M > > > > 128 > > > > > > Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64 > > > byte L1 line size that the 'cache' test reported? > > > > $ numactl -C 0 line -M 128K > > 64 > > $ numactl -C 3 line -M 128K > > 64 > > Ok, so this seems to confirm that the L1 uses 64 byte lines, while the L2 (or > possibly L3) uses 128 byte lines. > > On Wed, Jul 7, 2021 at 12:27 AM Bjorn Andersson > <bjorn.andersson@xxxxxxxxxx> wrote: > > > > I can confirm that MSM8996, and a few derivatives, has 128 byte cache lines. > > Ok, thanks. Assuming this is an outer cache and the L1 indeed has a smaller line > size, can you also confirm that this 128 byte lines are north of the point of > coherency? Finding this old documentation has been painful :) L0 I 64 byte cacheline L1 I 64 L1 D 64 L2 unified 128 (shared between the CPUs of a duplex) I believe L2 is within the POC, but I'm trying to dig up the old documentation to confirm. > > In other words, does the CTR_EL0.DminLine field also show 128 bytes > (in which case > it seems we already lost)? And if not, does a CPU store to the second half of a > 128 byte L2 line cause DMA data in the first half to be clobbered? Per the documentation I'm seeing, CTR_EL0.DminLine should show 128 bytes. I don't have hardware handy to confirm.