On Tue, 06 Jul 2021 15:30:34 +0100, Arnd Bergmann <arnd@xxxxxxxx> wrote: > > On Tue, Jul 6, 2021 at 3:44 PM Marc Zyngier <maz@xxxxxxxxxx> wrote: > > > > On 2021-07-06 14:33, Will Deacon wrote: > > > On Tue, Jul 06, 2021 at 02:29:07PM +0100, Robin Murphy wrote: > > > > > > I can't find much information about the original Kryo core at all... > > > > I have similar issues with my QDF2400. The UART, RTC and DMA controllers > > are all screaming at me. I'm confident that the UART doesn't do any > > DMA (it is handled by the SBSA driver), but the DMA controllers are > > probably doing what it says on the tin. > > But that's a server chip, surely the DMA controller is fully cache > coherent as required by SBSA? (please?) Remember that there is a SBSA level for each broken implementation (even my XGene is SBSA compliant!), so that doesn't mean much. > Maybe just a misannotation on the device node? Maybe. But given that whoever wrote the ACPI tables made sure that everything else was annotated as coherent, I doubt the DMA controllers being advertised as non-coherent is an accident. > > Do we know whether Falkor and Kryo share any part of their design? > > I'm fairly sure the Snapdragon 821 / msm8996 is not cache coherent. > > I can only speculate on how much got reused between the two, but > as Falkor was released only after they had already given up on > the full-custom Kryo core, it's plausible that it incorporates bits from > that one. In particular the cache controller is probably easy to reuse > even if the rest of it was a new design. I guess we'll never find out, and I'm probably one of the few still having some access to this HW (not even sure for how long anyway). I won't cry if we decide to pull the plug on it. M. -- Without deviation from the norm, progress is not possible.
