On 2021-07-06 14:33, Will Deacon wrote:
On Tue, Jul 06, 2021 at 02:29:07PM +0100, Robin Murphy wrote:
On 2021-07-06 11:26, Catalin Marinas wrote:
> On Tue, Jul 06, 2021 at 09:26:59AM +0000, Yassine Oudjana wrote:
> > In-Reply-To: <20210527124356.22367-1-will@xxxxxxxxxx>
> > > Reduce ARCH_DMA_MINALIGN to 64 bytes and allow the warning/taint to
> > > indicate if there are machines that unknowingly rely on this.
> >
> > The warning is being triggered on Qualcomm MSM8996, as well as the out-of-spec taint:
>
> Is this booting with ACPI or DT?
>
> > ------------[ cut here ]------------
> > rtc-pm8xxx 400f000.qcom,spmi:pmic@0:rtc@6000: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (64 < 128)
> > WARNING: CPU: 0 PID: 1 at arch/arm64/mm/dma-mapping.c:45 arch_setup_dma_ops+0xf8/0x10c
> [...]
> > This warning is triggered with nearly every driver probe, not only rtc-pm8xxx.
>
> I have a suspicion none of the reported devices actually do any DMA, so
> in practice it should be safe but we need to figure out why
> arch_setup_dma_ops() gets called.
It gets called because there's no straightforward way to know that a
platform device *isn't* DMA-capable, so we have to assume they are.
I would also assume that in a Qcom SoC there really are at least some
things
doing non-coherent DMA :(
Agreed, unless this is a CPU erratum and the line size is being
reported for
a cache beyond the PoC, then I think we're going to have to revert the
patch
reducing ARCH_DMA_MINALIGN after all.
I can't find much information about the original Kryo core at all...
I have similar issues with my QDF2400. The UART, RTC and DMA controllers
are all screaming at me. I'm confident that the UART doesn't do any
DMA (it is handled by the SBSA driver), but the DMA controllers are
probably doing what it says on the tin.
Do we know whether Falkor and Kryo share any part of their design?
M.
--
Jazz is not dead. It just smells funny...
