On Mon, Feb 08, 2021 at 08:00:06AM +0200, Baruch Siach wrote: > From: Balaji Prakash J <bjagadee@xxxxxxxxxxxxxx> > > DWC_USB3_GFLADJ and DWC_USB3_GUCTL registers contain options > to control the behavior of controller with respect to SOF and ITP. > The reset values of these registers are aligned for 19.2 MHz > reference clock source. This change will add option to override > these settings for reference clock other than 19.2 MHz > > Tested on IPQ6018 SoC based CP01 board with 24MHz reference clock. > > Signed-off-by: Balaji Prakash J <bjagadee@xxxxxxxxxxxxxx> > [ baruch: mention tested hardware ] > Signed-off-by: Baruch Siach <baruch@xxxxxxxxxx> > --- > .../devicetree/bindings/usb/dwc3.txt | 5 ++ Bindings should be split into a separate patch (1/2) so that the DT maintainers can review it easier. Also, always run checkpatch on your submissions before sending them out. thanks, greg k-h
