On 05-01-21, 17:56, Manivannan Sadhasivam wrote:
> Add qpic_nand node to support QPIC NAND controller on SDX55 platform.
> Since there is no "aon" clock in SDX55, a dummy clock is provided.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
> arch/arm/boot/dts/qcom-sdx55.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
> index 1b9b990ad0a2..1a6947753972 100644
> --- a/arch/arm/boot/dts/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
> @@ -41,6 +41,12 @@ pll_test_clk: pll-test-clk {
> #clock-cells = <0>;
> clock-frequency = <400000000>;
> };
> +
> + nand_clk_dummy: nand-clk-dummy {
Why dummy..?
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
Is this sleep clock of platform..?
> + };
> };
>
> cpus {
> @@ -178,6 +184,22 @@ qpic_bam: dma@1b04000 {
> status = "disabled";
> };
>
> + qpic_nand: nand@1b30000 {
> + compatible = "qcom,sdx55-nand";
> + reg = <0x01b30000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&rpmhcc RPMH_QPIC_CLK>,
> + <&nand_clk_dummy>;
> + clock-names = "core", "aon";
> +
> + dmas = <&qpic_bam 0>,
> + <&qpic_bam 1>,
> + <&qpic_bam 2>;
> + dma-names = "tx", "rx", "cmd";
> + status = "disabled";
> + };
> +
> tcsr_mutex_block: syscon@1f40000 {
> compatible = "syscon";
> reg = <0x1f40000 0x20000>;
> --
> 2.25.1
--
~Vinod
