Quoting Amit Nischal (2018-06-06 04:41:45)
> For some of the GDSCs, there is a requirement to enable/disable the
> few clocks before turning on/off the gdsc power domain. Add support
Why is there a requirement? Do the clks need to be in hw control mode or
they can't be turned off when the GDSC is off? It's hard for me to
understand with these vague statements.
> for the same by specifying a list of clk_hw pointers per gdsc and
> enable/disable them along with power domain on/off callbacks.
>
> Signed-off-by: Amit Nischal <anischal@xxxxxxxxxxxxxx>
> ---
> drivers/clk/qcom/gdsc.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/qcom/gdsc.h | 5 +++++
> 2 files changed, 49 insertions(+)
>
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index a077133..b6adca1 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -12,6 +12,8 @@
> */
>
> #include <linux/bitops.h>
> +#include <linux/clk.h>
Ugh.
> +#include <linux/clk-provider.h>
Both, really?
> #include <linux/delay.h>
> #include <linux/err.h>
> #include <linux/jiffies.h>
> @@ -208,11 +210,41 @@ static inline void gdsc_assert_reset_aon(struct gdsc *sc)
> regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
> GMEM_RESET_MASK, 0);
> }
> +
> +static int gdsc_clk_prepare_enable(struct gdsc *sc)
> +{
> + int i, ret;
> +
> + for (i = 0; i < sc->clk_count; i++) {
> + ret = clk_prepare_enable(sc->clk_hws[i]->clk);
> + if (ret) {
> + for (i--; i >= 0; i--)
> + clk_disable_unprepare(sc->clk_hws[i]->clk);
> + return ret;
> + }
> + }
> + return 0;
> +}
> +
Looks an awful lot like bulk_enable clk API.
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