After checking the DSPP units in the catalog vs the vendor devicetrees, link several DSPP units to the corresponding LM units. Each correction is submitted separately in order to be able to track and apply / skip them separately based on the feedback from Qualcomm. I think at this point only CrOS compositor actually uses CTM, so these changes do not need to be backported (none of the CrOS-enabled devices are touched by these patches). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> --- Changes in v2: - Expanded commit messages to mention the resulting effect (Johan) - Move the SDM670 fix to the top of the series - Link to v1: https://lore.kernel.org/r/20241216-dpu-fix-catalog-v1-0-15bf0807dba1@xxxxxxxxxx --- Dmitry Baryshkov (8): drm/msm/dpu: provide DSPP and correct LM config for SDM670 drm/msm/dpu: link DSPP_2/_3 blocks on SM8150 drm/msm/dpu: link DSPP_2/_3 blocks on SC8180X drm/msm/dpu: link DSPP_2/_3 blocks on SM8250 drm/msm/dpu: link DSPP_2/_3 blocks on SM8350 drm/msm/dpu: link DSPP_2/_3 blocks on SM8550 drm/msm/dpu: link DSPP_2/_3 blocks on SM8650 drm/msm/dpu: link DSPP_2/_3 blocks on X1E80100 .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 54 +++++++++++++++++++++- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 + .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 + .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 + 8 files changed, 66 insertions(+), 2 deletions(-) --- base-commit: d82c9281189d2b27642ede2760db495379503b86 change-id: 20241216-dpu-fix-catalog-63a3bc0db31e Best regards, -- Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
