On Mon, Oct 21, 2024 at 10:21:59PM +0200, Gabor Juhos wrote:
> Since both the 'alpha' and 'alpha_hi' members of the configuration is
> initialized with zero values, the output rate of the PLL will be the
> same whether alpha mode is enabled or not.
>
> Remove the initialization of the alpha* members to make it clear that
> alpha mode is not required to get the desired output rate.
>
> While at it, also add a comment to indicate the frequency the PLL runs
> at with the current configuration.
>
> No functional changes, the PLL runs at 1.2 GHz both before and after
> the change.
>
> Tested on Xiaomi Mi Router AX1800 (IPQ6018, out-of-tree board).
>
> Signed-off-by: Gabor Juhos <j4g8y7@xxxxxxxxx>
> ---
> drivers/clk/qcom/gcc-ipq6018.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> index ab0f7fc665a9790dd8edba0cf4b86c5c672a337d..d861191b0c85ccc105ac0e62d7a68210c621fc13 100644
> --- a/drivers/clk/qcom/gcc-ipq6018.c
> +++ b/drivers/clk/qcom/gcc-ipq6018.c
> @@ -4194,10 +4194,9 @@ static const struct alpha_pll_config ubi32_pll_config = {
> .test_ctl_hi_val = 0x4000,
> };
>
> +/* 1200 MHz configuration */
> static const struct alpha_pll_config nss_crypto_pll_config = {
> .l = 0x32,
> - .alpha = 0x0,
> - .alpha_hi = 0x0,
I'd say this serves documentation purposes: zero alpha value
> .config_ctl_val = 0x4001055b,
> .main_output_mask = BIT(0),
> .pre_div_val = 0x0,
> @@ -4206,7 +4205,6 @@ static const struct alpha_pll_config nss_crypto_pll_config = {
> .post_div_mask = GENMASK(11, 8),
> .vco_mask = GENMASK(21, 20),
> .vco_val = 0x0,
> - .alpha_en_mask = BIT(24),
This is okay
> };
>
> static struct clk_hw *gcc_ipq6018_hws[] = {
>
> --
> 2.47.0
>
--
With best wishes
Dmitry
