On Wed, 26 Jun 2024 at 06:03, Bjorn Andersson <andersson@xxxxxxxxxx> wrote:
>
> On Sat, Jun 22, 2024 at 04:36:20PM GMT, Robert Marko wrote:
> >
> > On 20. 06. 2024. 17:01, Chukun Pan wrote:
> > > The mmc controller of the IPQ6018 does not support HS400 mode.
> > > So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
> > >
> > > Signed-off-by: Chukun Pan <amadeus@xxxxxxxxxx>
> > > ---
> > > drivers/clk/qcom/gcc-ipq6018.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> > > index 7e69de34c310..6c764e3e2665 100644
> > > --- a/drivers/clk/qcom/gcc-ipq6018.c
> > > +++ b/drivers/clk/qcom/gcc-ipq6018.c
> > > @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
> > > F(96000000, P_GPLL2, 12, 0, 0),
> > > F(177777778, P_GPLL0, 4.5, 0, 0),
> > > F(192000000, P_GPLL2, 6, 0, 0),
> > > - F(384000000, P_GPLL2, 3, 0, 0),
> > > + F(200000000, P_GPLL0, 4, 0, 0),
> >
> > Hi,
> > Are you sure that 200MHz is even valid of a frequency, cause all IPQ SoC-s
> > use 192MHz for the HS200 mode instead.
> >
>
> If I'm parsing the docs correctly, 192MHz, 200MHz and 384MHz are a valid
> frequencies for the clock output, but the SDCC expects to receive 200MHz.
>
> > I would just drop the 384MHz frequency as datasheet clearly states that
> > HS400
> > is not supported.
> >
>
> I'll pick this patch as suggested. Please don't hesitate to send a
> follow up patch according to this suggestion if it turns out to be a
> better choice.
Since you have datasheet and 200MHz is a valid option that is fine
by me.
Regards,
Robert
>
> Regards,
> Bjorn
>
> > Regards,
> > Robert
> >
> > > { }
> > > };
