On 02/28, Archit Taneja wrote: > The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading > its current value from the NS register. > > Using the pre-divider wasn't really intended when creating these ops. > The pixel RCG was only intended to achieve fractional multiplication > provided in the pixel_table array. Leaving the pre-divider to the > existing register value results in a wrong pixel clock when the > bootloader sets up the display. This was left unidentified because > the IFC6410 Plus board on which this was verified didn't have a > bootloader that configured the display. > > Don't set the RCG pre-divider in freq_tbl to the existing NS register > value. Force it to 1 and only use the M/N counter to achieve the desired > fractional multiplication. > > Cc: John Stultz <john.stultz@xxxxxxxxxx> > Cc: Vinay Simha <vinaysimha@xxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Archit Taneja <architt@xxxxxxxxxxxxxx> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
