On Sun, Feb 28, 2016 at 2:07 AM, Archit Taneja <architt@xxxxxxxxxxxxxx> wrote:
> The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
> its current value from the NS register.
>
> Using the pre-divider wasn't really intended when creating these ops.
> The pixel RCG was only intended to achieve fractional multiplication
> provided in the pixel_table array. Leaving the pre-divider to the
> existing register value results in a wrong pixel clock when the
> bootloader sets up the display. This was left unidentified because
> the IFC6410 Plus board on which this was verified didn't have a
> bootloader that configured the display.
>
> Don't set the RCG pre-divider in freq_tbl to the existing NS register
> value. Force it to 1 and only use the M/N counter to achieve the desired
> fractional multiplication.
>
> Cc: John Stultz <john.stultz@xxxxxxxxxx>
> Cc: Vinay Simha <vinaysimha@xxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Archit Taneja <architt@xxxxxxxxxxxxxx>
> ---
> drivers/clk/qcom/clk-rcg.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
> index bfbb28f..67ce7c1 100644
> --- a/drivers/clk/qcom/clk-rcg.c
> +++ b/drivers/clk/qcom/clk-rcg.c
> @@ -638,7 +638,6 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
> return ret;
>
> src = ns_to_src(&rcg->s, ns);
> - f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;
>
> for (i = 0; i < num_parents; i++) {
> if (src == rcg->s.parent_map[i].cfg) {
> @@ -647,6 +646,9 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
> }
> }
>
> + /* bypass the pre divider */
> + f.pre_div = 1;
> +
> /* let us find appropriate m/n values for this */
> for (; frac->num; frac++) {
> request = (rate * frac->den) / frac->num;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
>
This one works for me on the nexus7
Tested-by: John Stultz <john.stultz@xxxxxxxxxx>
thanks
-john
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