On 24-04-18 13:33:19, Konrad Dybcio wrote:
> On 18.04.2024 12:51 PM, Abel Vesa wrote:
> > Currently, PLL0 is configured by the bootloader is the parent of the
> > mdp_clk_src. Reconfiguring it on probe leaves the PLL0 in "stand-by"
> > state (unlocked), which will trigger RCG child clocks to not update
> > their config,
>
> Sounds like this is the problem that should be fixed instead.
>
> which then breaks eDP on all x1e80100 boards. So rely
> > on the bootloader for now. Drop the config values as well. Also add
> > a comment to explain why the PLL0 is not configured alongside PLL1.
> >
> > Fixes: ee3f0739035f ("clk: qcom: Add dispcc clock driver for x1e80100")
> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> > ---
>
> This works, because you have (at least) partially configured hardware, but
> we shouldn't assume this to be the case.
OK, I think we should be safe to follow trion's approach instead then.
https://lore.kernel.org/all/20211123162508.153711-1-bjorn.andersson@xxxxxxxxxx/
>
> Konrad
