On Mon, Dec 19, 2022 at 09:51:40PM +0100, Konrad Dybcio wrote:
>
>
> On 19.12.2022 20:14, Manivannan Sadhasivam wrote:
> > Both PCIe0 and PCIe1 controllers are capable of receiving MSIs from
> > endpoint devices using GIC-ITS MSI controller. Add support for it.
> >
> > Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the
> > msi-map-mask of 0xff00, all the 32 devices under these two busses can
> > share the same Device ID.
> >
> > The GIC-ITS MSI implementation provides an advantage over internal MSI
> > implementation using Locality-specific Peripheral Interrupts (LPI) that
> > would allow MSIs to be targeted for each CPU core.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > ---
> This breaks PCIe Wi-Fi on Xperia 1 IV:
>
> [ 32.711199] ath11k_pci 0000:01:00.0: Adding to iommu group 5
> [ 32.713738] ath11k_pci 0000:01:00.0: BAR 0: assigned [mem 0x60400000-0x605fffff 64bit]
> [ 32.715447] ath11k_pci 0000:01:00.0: MSI vectors: 32
> [ 32.715485] ath11k_pci 0000:01:00.0: wcn6855 hw2.1
> [ 32.873873] mhi mhi0: Requested to power ON
> [ 32.873896] mhi mhi0: Power on setup success
> [ 65.161798] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x91517088, fsynr=0x640001, cbfrsynra=0x1c00, cb=5
>
Thanks a lot for testing! Can you please share the full dmesg log?
Thanks,
Mani
>
> Konrad
> > arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++------
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > index 570475040d95..276ceba4c247 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > @@ -1733,9 +1733,9 @@ pcie0: pci@1c00000 {
> > ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> > <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
> >
> > - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "msi";
> > - #interrupt-cells = <1>;
> > + msi-map = <0x0 &gic_its 0x5980 0x1>,
> > + <0x100 &gic_its 0x5981 0x1>;
> > + msi-map-mask = <0xff00>;
> > interrupt-map-mask = <0 0 0 0x7>;
> > interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > @@ -1842,9 +1842,9 @@ pcie1: pci@1c08000 {
> > ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
> > <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
> >
> > - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "msi";
> > - #interrupt-cells = <1>;
> > + msi-map = <0x0 &gic_its 0x5a01 0x1>,
> > + <0x100 &gic_its 0x5a00 0x1>;
> > + msi-map-mask = <0xff00>;
> > interrupt-map-mask = <0 0 0 0x7>;
> > interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
--
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