On 12/12/2022 13:33, Manivannan Sadhasivam wrote:
> The LLCC block has several banks each with a different base address
> and holes in between. So it is not a correct approach to cover these
> banks with a single offset/size. Instead, the individual bank's base
> address needs to be specified in devicetree with the exact size.
>
> On SC7180, there is only one LLCC bank available. So only change needed is
> to remove the reg-names property from LLCC node to conform to the binding.
>
> The driver is expected to parse the reg field based on index to get the
> addresses of each LLCC banks.
>
> Cc: <stable@xxxxxxxxxxxxxxx> # 5.6
Oh, no, there is no single bug here. Binding from v5.6+ (which cannot be
changed) required/defined such reg-names. This is neither a bug nor
possible to backport.
> Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Drop.
> Reported-by: Parikshit Pareek <quic_ppareek@xxxxxxxxxxx>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index f71cf21a8dd8..b0d524bbf051 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -2759,7 +2759,6 @@ dc_noc: interconnect@9160000 {
> system-cache-controller@9200000 {
> compatible = "qcom,sc7180-llcc";
> reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
> - reg-names = "llcc_base", "llcc_broadcast_base";
That's an ABI break...
> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> };
>
Best regards,
Krzysztof
