On Tue, Dec 13, 2022 at 09:04:39PM +0530, Shazad Hussain wrote:
>
>
> On 12/13/2022 8:58 PM, Johan Hovold wrote:
> > On Tue, Dec 13, 2022 at 10:12:57AM -0500, Brian Masney wrote:
> >> On Tue, Dec 13, 2022 at 03:54:05PM +0100, Johan Hovold wrote:
> >>> Note that the node is labelled qup2_i2c5 and not qup_i2c5.
> >>>
> >>> That is, the QUP nodes are labelled using two indices, and specifically
> >>>
> >>> qup2_i2c5
> >>>
> >>> would be another name for
> >>>
> >>> qup_i2c21
> >>>
> >>> if we'd been using such a flat naming scheme (there are 8 engines per
> >>> QUP).
> >>>
> >>> So there's nothing wrong with how these nodes are currently named, but
> >>> mixing the two scheme as you are suggesting would not be correct.
> >>
> >> Hi Johan,
> >>
> >> What would I use for the name in the aliases section? Right now I have:
> >>
> >> aliases {
> >> i2c18 = &qup2_i2c18;
> >> }
> >>
> >> So qup2_i2c18 becomes qup2_i2c2. Would I use the flat naming scheme for
> >> the alias like so?
> >>
> >> aliases {
> >> i2c18 = &qup2_i2c2;
> >> }
> >
> > Or perhaps the i2c controllers should use a zero-based index instead of
> > being named after the serial engines (e.g. as we do for the console
> > uart).
> >
> > How are they named in the schematics?
>
> We should use from 0 to N.
With N being 23 after the number of serial engines, or the number of
available i2c buses on a particular board minus one?
Johan
