On Tue, Sep 20, 2022 at 12:15:56PM +0530, Vinod Koul wrote:
> On 10-09-22, 12:08, Manivannan Sadhasivam wrote:
> > In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
> > QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
> > and QPHY_V5_PCS_EQ_CONFIG3.
> >
> > This causes high latency when ASPM is enabled, so fix it!
> >
> > Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > ---
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > index 61a44519f969..cca6455ec98c 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > @@ -11,7 +11,7 @@
> > #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
> > #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> > #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> > -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
> > -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
Why are you removing these defines? (They are correct for sc8280xp.)
> > +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
> > +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
>
> This conflicts with c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy")
>
> where QPHY_V5_PCS_EQ_CONFIG5 was added as 0x1e0
>
> Do we have a different v5 for SM8450 and SC8280XP?
I can confirm that the PCS_EQ_CONFIG defines added for sc8280xp matches
the vendor's headers for both the combo and USB PHYs.
Johan
