Hi Dm On Wed, 19 Jan 2022 at 11:45, Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> wrote: > > On Wed, 19 Jan 2022 at 12:42, Loic Poulain <loic.poulain@xxxxxxxxxx> wrote: > > > > According to downstream driver, byte intf clk rate should be half the > > byte clk only with DSI PHY verion above 2.0 (14nm): > > https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dsi/dsi_display.c?h=LA.UM.8.12.3.1#n3991 > > This is a bit strange. We have other 14nm DSI PHYs, which are thought > to be working (msm8996, sdm660). Not tested by me, though. > And msm8916 has 28nm-lp, which according to CAF's patch should also use Yes, It's not clear to me if this clock configuration is just a recommendation or a requirement. All I can say is that it fixes DSI issue on QCM2290 14nm, so maybe I should be more conservative and restrict this behaviour to QCM2290 phy only? [...] > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > index 7414966..f4849e6 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > > @@ -897,6 +897,9 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) > > > > phy->vco_hw = &pll_14nm->clk_hw; > > > > + /* For PHY version <= 2.0 (14nm), byte_intf_clk = byte_clk */ > > + phy->no_byte_intf_clk_div = true; > > This setting can go into constant phy configuration instead. And also > note that there are other <= 2.0 PHYs (20nm, 28nm). > Do they share this property? According to downstream, yes, but I can not test on other PHYs. Regards, Loic
