Add a new iommu domain attribute that can be used to enable cache
coherent hardware table walks (HTW) by the SMMU. HTW might be supported
by the SMMU HW but depending on the use case and the usage of the SMMU
in the SoC it might not be always beneficial to always turn on coherent HTW for
all domains/iommu's.
Signed-off-by: Olav Haugan <ohaugan@xxxxxxxxxxxxxx>
---
drivers/iommu/msm_iommu-v1.c | 16 ++++++++++++++++
include/linux/iommu.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/iommu/msm_iommu-v1.c b/drivers/iommu/msm_iommu-v1.c
index 2c574ef..e163ffc 100644
--- a/drivers/iommu/msm_iommu-v1.c
+++ b/drivers/iommu/msm_iommu-v1.c
@@ -1456,8 +1456,16 @@ static int msm_domain_get_attr(struct iommu_domain *domain,
enum iommu_attr attr, void *data)
{
s32 ret = 0;
+ struct msm_iommu_priv *priv = domain->priv;
switch (attr) {
+ case DOMAIN_ATTR_COHERENT_HTW:
+ {
+ s32 *int_ptr = (s32 *) data;
+
+ *int_ptr = priv->pt.redirect;
+ break;
+ }
default:
pr_err("Unsupported attribute type\n");
ret = -EINVAL;
@@ -1471,8 +1479,16 @@ static int msm_domain_set_attr(struct iommu_domain *domain,
enum iommu_attr attr, void *data)
{
s32 ret = 0;
+ struct msm_iommu_priv *priv = domain->priv;
switch (attr) {
+ case DOMAIN_ATTR_COHERENT_HTW:
+ {
+ s32 *int_ptr = (s32 *) data;
+
+ priv->pt.redirect = *int_ptr;
+ break;
+ }
default:
pr_err("Unsupported attribute type\n");
ret = -EINVAL;
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 63dca6d..6d9596d 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -81,6 +81,7 @@ enum iommu_attr {
DOMAIN_ATTR_FSL_PAMU_STASH,
DOMAIN_ATTR_FSL_PAMU_ENABLE,
DOMAIN_ATTR_FSL_PAMUV1,
+ DOMAIN_ATTR_COHERENT_HTW,
DOMAIN_ATTR_MAX,
};
--
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