On Tue, 2010-06-29 at 21:03 +0200, Martijn Stolk wrote: > No worries. I wanted to isolate what specifically fixes the problem > myself in order to make a minimal patch. I'm also hoping for some help > regarding information, as I don't have access to official QSD8250 > documentation. > > I've found the key register that differs between between how it is > initialized for Windows CE and for Linux, and solves the problem for us. > It is the Auxilliary Control Register (cp15, 0, c1, c0, 1). > > For Windows CE it is initialized to 0x002C0077 > (=0b00000000001011000000000001110111) > For Linux it is initialized to 0x000C0037 > (=0b00000000000011000000000000110111) > > The following page explains this register for the Cortex-A8, the ARM > core on which the QSD8250 is based: > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Bgbffjhh.html > > The 7th bit (bit 6 on that page) controls the behaviour of the > Invalidate All & by MVA instructions. It needs to be disabled for Linux. > > The 22nd bit, however, is in an area marked as "reserved" on that page. > I am very curious what this bit does. Maybe this reserved area is > documented in QSD8250 documentation? Could anyone provide clearity about > this bit? You found that you needed both of these set? One or the other wasn't enough. I'm not sure that we can open talk about what this 22nd bit does, so I'd just set it like you have it and not worry about it. Daniel -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
