* Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote: > > > On Wed, 18 Feb 2009, Ingo Molnar wrote: > > > > an off-list comment pointed out this piece of information as > > well: > > > > http://www.sandpile.org/ia32/coherent.htm > > > > A WRMSR to one of the x2APIC MSRs (0000_0800h...0000_0BFFh) is > > not guaranteed to be serializing. > > > > So i suspect we should just enclose it in smp_mb() pairs to make > > sure it's a full barrier in both directions? > > Why would we care about "both directions"? > > I think putting an sfence _before_ the wrmsr (and not even all > of them - just put it in front of the "send IPI" sequence) > should be fine. Any other ordering sounds like just > unnecessary overhead to me. > > We do want this to be low-overhead, even if we probably don't > care _that_ much. yeah, you are right, making sure prior stores become visible should be the only worry here. Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
