On Tue, Feb 17, 2009 at 02:39:10PM -0800, Paul E. McKenney wrote: > On Tue, Feb 17, 2009 at 10:45:18PM +0100, Oleg Nesterov wrote: > > > If all of the above is executed by the same task, tripping the BUG_ON() > > > means either a compiler or CPU bug. > > > > I think you misunderstood... > > > > smp_send_xxx() sends the ipi to another CPU, and smp_xxx_interrupt() is > > the handler. > > You are right, I did miss that completely. :-/ > > I have seen hardware in which the IPI could beat the cache invalidation > from the sending CPU to the interrupted CPU, and in which one or both of > the CPUs would have to execute special cache-flush/invalidation/whatever > instructions for the interrupted CPU to have a consistent view of the > data (in your example, "COND"). > > But we had a little chat with the hardware designers, and in subsequent > hardware, the IPI interacted with the cache-coherence protocol so as to > prevent the above bug from firing. However, this was x86-based hardware, > which orders writes. Weakly ordered systems would likely need a memory > barrier somewhere, whether as shown above or buried in the smp_send_xxx() > primitive. I agree with you both that we *should* make arch interrupt code do the ordering, but given the subtle lockups on some architectures in this new code, I didn't want to make it significantly weaker... Though perhaps it appears that I have, if I have removed an smp_mb that x86 was relying on to emit an mfence to serialise the apic. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
