ok, it's documented:
Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3A:
System Programming Guide, Part 1
9.5.3 MSR Access in x2APIC Mode
To allow for efficient access to the APIC registers in x2APIC
mode, the serializing semantics of WRMSR are relaxed when
writing to the APIC registers. Thus, system software should not
use “WRMSR to APIC registers in x2APIC mode” as a serializing
instruction. Read and write accesses to the APIC registers will
occur in program order. A WRMSR to an APIC register may
complete before all preceding stores are globally visible;
software can prevent this by inserting a serializing
instruction or MFENCE before the WRMSR.
Ingo
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