On Sat, 18 Oct 2008, Paul Mackerras wrote: > > Not sure what you mean by causal consistency, but I assume it's the > same as saying that barriers give cumulative ordering, as described on > page 413 of the Power Architecture V2.05 document at: I'm pretty sure that everybody but alpha is ok. And alpha needs the smp_read_barrier_depends() not because it doesn't really support causality, but because each CPU internally doesn't guarantee that they handle the cache invalidates in-order without a barrier. So without the smp_read_barrier_depends(), alpha will actually have the proper causal relationships (cachelines will move to exclusive state on CPU0 in the right order and others will see the causality), but because CPU2 may see the stale data from not even having invalidated the "anon_vma.initialized" because the cache invalidation queue hadn't been flushed in order. Alpha is insane. And the odd man out. Linus -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
