Nick Piggin writes: > But after thinking about this a bit more, I think Linux would be > broken all over the map under such ordering schemes. I think we'd > have to mandate causal consistency. Are there any architectures we > run on where this is not guaranteed? (I think recent clarifications > to x86 ordering give us CC on that architecture). > > powerpc, ia64, alpha, sparc, arm, mips? (cced linux-arch) Not sure what you mean by causal consistency, but I assume it's the same as saying that barriers give cumulative ordering, as described on page 413 of the Power Architecture V2.05 document at: http://www.power.org/resources/reading/PowerISA_V2.05.pdf The ordering provided by sync, lwsync and eieio is cumulative (see pages 446 and 448), so we should be OK on powerpc AFAICS. (The cumulative property of eieio only applies to accesses to normal system memory, but that should be OK since we use sync when we want barriers that affect non-cacheable accesses as well as cacheable.) Paul. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
