On Tue, Dec 04, 2018 at 06:55:41PM +0100, Rafael J. Wysocki wrote: > On Tuesday, December 4, 2018 12:20:48 PM CET Mika Westerberg wrote: > > Gigabyte X299 DESIGNARE EX motherboard has one PCIe root port that is > > connected to an Alpine Ridge Thunderbolt controller. This port has slot > > implemented bit set in the config space but other than that it is not > > hotplug capable in the sense we are expecting in Linux (it has > > dev->is_hotplug_bridge set to 0): > > > > 00:1c.4 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5 > > Bus: primary=00, secondary=05, subordinate=46, sec-latency=0 > > Memory behind bridge: 78000000-8fffffff [size=384M] > > Prefetchable memory behind bridge: 00003800f8000000-00003800ffffffff [size=128M] > > ... > > Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 > > ... > > SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- > > Slot #8, PowerLimit 25.000W; Interlock- NoCompl+ > > SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- > > Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- > > SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- > > Changed: MRL- PresDet+ LinkState+ > > > > This system is using ACPI based hotplug to notify the OS that it needs > > to rescan the PCI bus (ACPI hotplug). > > > > If there is nothing connected in any of the Thunderbolt ports the root > > port will not have any runtime PM active children and is thus > > automatically runtime suspended pretty soon after boot by PCI PM core. > > Now, when a device is connected the BIOS SMI handler responsible for > > enumerating newly added devices is not able to find anything because the > > port is in D3. > > > > Prevent this from happening by blacklisting PCI power management of this > > particular Gigabyte system. > > > > Reported-by: Kedar A Dongre <kedar.a.dongre@xxxxxxxxx> > > Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> > > --- > > I checked booting Windows on the same system and it does not put any of the > > PCIe root ports to low power states so there is no issue in Windows. I'm > > also quite certain Windows does not have similar blacklist. > > Well, that only means that Windows uses a different approach to decide whether > or not to use PCI PM on PCIe root ports (but we knew that that would be the > case upfront, didn't we?). Indeed we did. > > I wonder if our pci_bridge_d3_possible() heuristics would need to be > > refined somehow? At least if this blacklist starts growing. > > Because Windows uses a different approach here, there will be systems for > which Linux will decide to use PCI PM with PCIe root ports and Windows > won't (or vice versa). That will cause Linux to use configurations that > have not been validated against Windows, so it is likely that some of them > will not work. Hence, the need for a blacklist is not a surprise really. Fair enough :) > So > > Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx> Thanks! > BTW, what version of Windows you have tested? I only tested Windows 10 1803.
