Re: [PATCH 0/7] Resume BYT/CHT LPSS I2C controller before the iGPU

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On 09/20/2018 11:48 AM, Mika Westerberg wrote:
On Thu, Sep 20, 2018 at 10:07:01AM +0200, Rafael J. Wysocki wrote:
I forgot to mention that I've tested this series on the following device
which had the mentioned errors:

GPD win:
CHT device with a Whiskey Cove PMIC, PMIC I2C bus free for kernel use

And on the following other 3 devices to make sure that I covered all
combinations of BYT/CHT and PMIC with/without its I2C bus shared with
the PUNIT:

Chuwi Hi8 Pro:
CHT device with an AXP288 PMIC, with its I2C bus shared between the PUNIT and the kernel

Asus T100TA:
BYT device with a Crystal Cove PMIC, PMIC I2C bus free for kernel use

Peaq C1010 2-in-1:
BYT device with an AXP288 PMIC, with its I2C bus shared between the PUNIT and the kernel

And all 4 work fine with this series applied.

OK

It looks reasonable to me overall, but I'll give Mika/Andy and others some
time to leave comments if any.

Looks good to me as well. Nice work Hans! :)

I tested the set on a BYT based MRD7 with shared I2C bus and on a CHT which I don't know. Both devices suspended and resumed fine before the set. Maybe my test setup with only VGA console doesn't stress enough? Anyway I didn't notice any regression either.

Tested-by: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx>



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