On Wed, Mar 20, 2024 at 09:12:11PM -0700, Drew Fustini wrote: > On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote: > > On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote: > > > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote: > > > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote: > > > > > This series enables the support for "Collaborative Processor Performance > > > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > > > > > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > > > > > > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > > > > > enable this, is available at [2]. > > > > > > > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > > > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > > > > > > > > > The series is based on the LPI support series. > > > > > Based-on: 20240118062930.245937-1-sunilvl@xxxxxxxxxxxxxxxx > > > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@xxxxxxxxxxxxxxxx/) > > > > > > > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be > > > > used for this CPPC series too? > > > > > > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which > > > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD"). > > > I've built that but I still see 'SBI CPPC extension NOT detected!!' in > > > the Linux boot log. > > > > > > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because > > > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call > > > sbi_cppc_set_device(), so I am uncertain how it is possible for it to > > > work. Is there an opensbi branch I should be using? > > > > > > Thanks, > > > Drew > > > > > > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream > > > > Please use below branches for qemu and opensbi. These are just dummy > > objects/interfaces added to test the kernel change which are otherwise > > platform specific features. > > > > https://github.com/vlsunil/qemu/tree/lpi_cppc_exp > > https://github.com/vlsunil/opensbi/tree/cppc_exp > > I know the opensbi branch is just for the purpose of testing the kernel > driver. However, I am new to ACPI and I am trying to understand how a > real system might work. > > The _CPC register address encoding in the RISC-V FFH spec enables the > SBI CPPC register ID to be specified. But how would SBI firmware know > what physical address corresponds to the CPPC register? > > If sbi_cppc_test_write() [1] was implemented for a real system, then how > would it know what physical address to write to for a CPPC register like > SBI_CPPC_DESIRED_PERF? > The SBI extension provides an abstraction to access the CPPC registers. SBI implementation for the platform should be aware of how to access a particular register in the back end when it supports the extension. Regards, Sunil
