On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote: > This series enables the support for "Collaborative Processor Performance > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > enable this, is available at [2]. > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > The series is based on the LPI support series. > Based-on: 20240118062930.245937-1-sunilvl@xxxxxxxxxxxxxxxx > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@xxxxxxxxxxxxxxxx/) Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be used for this CPPC series too? Thanks, Drew
