On 08/23/2010 03:48 PM, Avi Kivity wrote:
On 08/23/2010 04:29 PM, Paolo Bonzini wrote:
On 08/23/2010 01:06 PM, Avi Kivity wrote:
Many x86 instructions come in pairs - byte and word variants where bit 0
of the opcode determines operand size. Use this to simplify the decode
tables.
Many actually come in quadruples, bit 0 is the size and bit 1 says
which of ModRM and REG is the destination.
example:
D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
Right. We can't exploit those yet.
What about this? It wouldn't work for things such as SrcAcc, but it
would still reap most of the benefit:
#define D4modrm(x) \
D2bv(DstMem | SrcReg | ModRM | (x)), \
D2bv(DstReg | SrcMem | ModRM | ((x) & ~Lock))
e.g.
- ALU block -> D4modrm(Lock)
- 0x88-0x8b -> D4modrm(Mov)
Paolo
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