On 08/23/2010 05:04 PM, Paolo Bonzini wrote:
On 08/23/2010 03:48 PM, Avi Kivity wrote:
On 08/23/2010 04:29 PM, Paolo Bonzini wrote:
On 08/23/2010 01:06 PM, Avi Kivity wrote:
Many x86 instructions come in pairs - byte and word variants where
bit 0
of the opcode determines operand size. Use this to simplify the decode
tables.
Many actually come in quadruples, bit 0 is the size and bit 1 says
which of ModRM and REG is the destination.
example:
D2bv(DstMem | SrcReg | ModRM | Lock), D2bv(DstReg | SrcMem | ModRM),
Right. We can't exploit those yet.
What about this? It wouldn't work for things such as SrcAcc, but it
would still reap most of the benefit:
#define D4modrm(x) \
D2bv(DstMem | SrcReg | ModRM | (x)), \
D2bv(DstReg | SrcMem | ModRM | ((x) & ~Lock))
It's fine except for the name. "bv" stands for the single letter flags
Intel gave to byte and word operations so it's somewhat descriptive.
Maybe we could call it ALU4() and pretend that mov is an ALU
instruction. We could also do an ALU6() for the ALU block.
A really clever macro could probably compress the entire table into a
single line.
e.g.
- ALU block -> D4modrm(Lock)
- 0x88-0x8b -> D4modrm(Mov)
--
error compiling committee.c: too many arguments to function
--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
