On 2/12/24 04:52, Chao Gao wrote: >>>> /* >>>> * Before returning from TDH.VP.ENTER, the TDX Module assigns: >>>> * XCR0 to the TD’s user-mode feature bits of XFAM (bits 7:0, 9) >>>> * IA32_XSS to the TD's supervisor-mode feature bits of XFAM (bits 8, 16:10) > > TILECFG state (bit 17) and TILEDATA state (bit 18) are also user state. Are they > cleared unconditionally? Bit 17 and 18 should also be in TDX_XFAM_XCR0_MASK TDX Module does define them, from TDX Module sources: #define XCR0_USER_BIT_MASK 0x000602FF Thanks for spotting that! > >>>> */ >>>> #define TDX_XFAM_XCR0_MASK (GENMASK(7, 0) | BIT(9)) >>>> #define TDX_XFAM_XSS_MASK (GENMASK(16, 10) | BIT(8)) >>>> #define TDX_XFAM_MASK (TDX_XFAM_XCR0_MASK | TDX_XFAM_XSS_MASK)
