On Thu, Jan 11, 2024, Paolo Bonzini wrote: > On Wed, Jan 10, 2024 at 1:23 AM Sean Christopherson <seanjc@xxxxxxxxxx> wrote: > > Add a VMX flag in /proc/cpuinfo, ept_5level, so that userspace can query > > whether or not the CPU supports 5-level EPT paging. > > I think this is a good idea independent of the selftests issue. > > For selftests, we could get similar info from the feature MSR > mechanism, i.e. KVM_GET_MSRS(MSR_IA32_VMX_EPT_VPID_CAP), but only on > Intel and only if nested virtualization is enabled, so that's > inferior. > > A better idea for selftests is to add a new KVM_CAP_PHYS_ADDR_SIZE, > which could be implemented by all architectures and especially by both > x86 vendors. Doh. I was thinking this wouldn't be a problem on AMD, but a guest can generate 52-bit GPAs even without LA57. > However, I am not sure for example if different VM types (read: TDX?) could > have different maximum physical addresses, and that would have to be taken > into consideration when designing the API.
