On Wed, Jan 10, 2024 at 1:23 AM Sean Christopherson <seanjc@xxxxxxxxxx> wrote: > Add a VMX flag in /proc/cpuinfo, ept_5level, so that userspace can query > whether or not the CPU supports 5-level EPT paging. I think this is a good idea independent of the selftests issue. For selftests, we could get similar info from the feature MSR mechanism, i.e. KVM_GET_MSRS(MSR_IA32_VMX_EPT_VPID_CAP), but only on Intel and only if nested virtualization is enabled, so that's inferior. A better idea for selftests is to add a new KVM_CAP_PHYS_ADDR_SIZE, which could be implemented by all architectures and especially by both x86 vendors. However, I am not sure for example if different VM types (read: TDX?) could have different maximum physical addresses, and that would have to be taken into consideration when designing the API. Paolo > tip-tree folks, this is obviously not technically KVM code, but I'd like to > take this through the KVM tree so that we can use the information to fix > KVM selftests (hopefully this cycle). > > arch/x86/include/asm/vmxfeatures.h | 1 + > arch/x86/kernel/cpu/feat_ctl.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/vmxfeatures.h b/arch/x86/include/asm/vmxfeatures.h > index c6a7eed03914..266daf5b5b84 100644 > --- a/arch/x86/include/asm/vmxfeatures.h > +++ b/arch/x86/include/asm/vmxfeatures.h > @@ -25,6 +25,7 @@ > #define VMX_FEATURE_EPT_EXECUTE_ONLY ( 0*32+ 17) /* "ept_x_only" EPT entries can be execute only */ > #define VMX_FEATURE_EPT_AD ( 0*32+ 18) /* EPT Accessed/Dirty bits */ > #define VMX_FEATURE_EPT_1GB ( 0*32+ 19) /* 1GB EPT pages */ > +#define VMX_FEATURE_EPT_5LEVEL ( 0*32+ 20) /* 5-level EPT paging */ > > /* Aggregated APIC features 24-27 */ > #define VMX_FEATURE_FLEXPRIORITY ( 0*32+ 24) /* TPR shadow + virt APIC */ > diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c > index 03851240c3e3..1640ae76548f 100644 > --- a/arch/x86/kernel/cpu/feat_ctl.c > +++ b/arch/x86/kernel/cpu/feat_ctl.c > @@ -72,6 +72,8 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) > c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_AD); > if (ept & VMX_EPT_1GB_PAGE_BIT) > c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_1GB); > + if (ept & VMX_EPT_PAGE_WALK_5_BIT) > + c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_5LEVEL); > > /* Synthetic APIC features that are aggregates of multiple features. */ > if ((c->vmx_capability[PRIMARY_CTLS] & VMX_F(VIRTUAL_TPR)) && > > base-commit: 1c6d984f523f67ecfad1083bb04c55d91977bb15 > -- > 2.43.0.472.g3155946c3a-goog
