When running pmu test on Intel Sapphire Rapids, we found several failures are encountered, such as "llc misses" failure, "all counters" failure and "fixed counter 3" failure. Intel Sapphire Rapids introduces new fixed counter 3, total PMU counters including GP and fixed counters increase to 12 and also optimizes cache subsystem. All these changes make the original assumptions in pmu test be unavailable any more on Sapphire Rapids. Patches 2-4 fixes these failures, especially patch 2 improves current loop() function and ensure the LLC/branch misses are always be triggered and don't depend on the possibility like before, patch 1 removes the duplicate code and patch 5 adds asserts to ensure pre-defined fixed events are matched with HW fixed counters. Plese note 1) this patchset depends on the Kernel patches "Enable topdown slots event in vPMU" 2) this patchset is only tested on Intel Sapphire rapids platform, the tests on other platforms are welcomed. Dapeng Mi (4): x86: pmu: Improve loop() to force to generate llc/branch misses x86: pmu: Enlarge cnt array length to 64 in check_counters_many() x86: pmu: Support validation for Intel PMU fixed counter 3 x86: pmu: Add asserts to warn inconsistent fixed events and counters Xiong Zhang (1): x86: pmu: Remove duplicate code in pmu_init() lib/x86/pmu.c | 5 ----- x86/pmu.c | 54 +++++++++++++++++++++++++++++++-------------------- 2 files changed, 33 insertions(+), 26 deletions(-) base-commit: bfe5d7d0e14c8199d134df84d6ae8487a9772c48 -- 2.34.1
