The topdown slots event counts the total number of available slots for an unhalted logical processor. Software can use this event to calculate the topdown metrics by collaborating with IA32_PERF_METRICS MSR. Since Intel Icelake CPU starts, the topdown slots event can be programmed both on GP counters or the exclusive fixed counter 3 but with different event & umask code. The event with code (event=0xa4,umask=0x01) is an architectural event which is represented in CPUID.0AH.EBX and can be programed on any GP counter. Besides, Intel PMU from Icelake introduces a new fixed counter (fixed counter 3) to count/sample todpown slots event so the precious GP counters can be saved. The fixed counter 3 uses an exclusive code (event=0x00,umask=0x04) to count/sample the slots event. Actually this patchset is a portion of the patchset "Enable fixed counter 3 and topdown perf metrics for vPMU"[1]. As this original patchset needs to make some fundamental changes on perf code and cause big arguments, it leads to the vPMU topdown metrics patchset is hard to be merged in current vPMU emulation framework. The patches of enabling topdown slots event is simple and doesn't touch any perf code. Moreover topdown slots event as an independent feature is still valuable even though in no topdown metrics cases, some perf metrics depend on slots event and need to be derived from slots event. Thus the patches of enabling slots event is extracted as an independent patchset and resend. Ref: 1. https://lore.kernel.org/all/20230927033124.1226509-1-dapeng1.mi@xxxxxxxxxxxxxxx/T/ Dapeng Mi (2): KVM: x86/pmu: Add Intel CPUID-hinted TopDown slots event KVM: x86/pmu: Support PMU fixed counter 3 arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 12 ++++++++++++ arch/x86/kvm/x86.c | 4 ++-- 3 files changed, 15 insertions(+), 3 deletions(-) base-commit: 35dcbd9e47035f98f3910ae420bf10892c9bdc99 -- 2.34.1
