Avi Kivity wrote: > On 04/14/2010 04:19 PM, Jan Kiszka wrote: >> Avi Kivity wrote: >> >>> On 04/14/2010 03:58 PM, Jan Kiszka wrote: >>> >>>>> The TSS descriptor (gate doesn't have a size). But isn't it possible to >>>>> have a 32-bit TSS with a 16-bit CS/SS? >>>>> >>>>> >>>> Might be possible, but will cause troubles as the spec says: >>>> >>>> "The error code is pushed on the stack as a doubleword or word >>>> (depending on the default interrupt, trap, or task gate size)." >>>> >>>> >>> My guess is that this is an error and that the 32-bitness of a TSS only >>> refers to the format of the TSS, and has nothing to do with the code >>> that actually runs. I'll ask Intel about it. Meanwhile this can be >>> applied, if there's a problem with 16-bit exception handlers running >>> through a 32-bit task referenced by a task gate in the IDT, it can be >>> fixed later. >>> >> Go ahead. But architecturally this looks fairly consistent to me as the >> processor simply derives the error code width from the corresponding >> entry in the IDT. >> > > You are correct (though the entry isn't in the IDT!) Yeah, right (this stuff keeps on hurting my brain). Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
