On Wed, 29 Mar 2023 14:50:50 +0200 Nico Boehr <nrb@xxxxxxxxxxxxx> wrote: > Quoting Janosch Frank (2023-03-28 16:13:04) > > On 3/27/23 10:21, Nico Boehr wrote: > > > This is to prepare for running guests without MSO/MSL, which is > > > currently not possible. > > > > > > We already have code in sie64a to setup a guest primary ASCE before > > > entering SIE, so we can in theory switch to the page tables which > > > translate gpa to hpa. > > > > > > But the host is running in primary space mode already, so changing the > > > primary ASCE before entering SIE will also affect the host's code and > > > data. > > > > > > To make this switch useful, the host should run in a different address > > > space mode. Hence, set up and change to home address space mode before > > > installing the guest ASCE. > > > > > > The home space ASCE is just copied over from the primary space ASCE, so > > > no functional change is intended, also for tests that want to use > > > MSO/MSL. If a test intends to use a different primary space ASCE, it can > > > now just set the guest.asce in the save_area. > > > > > [...] > > > + /* set up home address space to match primary space */ > > > + old_cr13 = stctg(13); > > > + lctlg(13, stctg(1)); > > > + > > > + /* switch to home space so guest tables can be different from host */ > > > + psw_mask_set_bits(PSW_MASK_HOME); > > > + > > > + /* also handle all interruptions in home space while in SIE */ > > > + lowcore.pgm_new_psw.mask |= PSW_MASK_DAT_HOME; > > > > > + lowcore.ext_new_psw.mask |= PSW_MASK_DAT_HOME; > > > + lowcore.io_new_psw.mask |= PSW_MASK_DAT_HOME; > > We didn't enable DAT in these two cases as far as I can see so this is > > superfluous or we should change the mmu code. Also it's missing the svc > > and machine check. > > Right. Is there a particular reason why we only run DAT on for PGM ints? a fixup handler for PGM it might need to run with DAT on (e.g. to access data that is not identity mapped), whereas for other interrupts it's not needed (at least not yet ;) ) > > > The whole bit manipulation thing looks a bit crude. It might make more > > sense to drop into real mode for a few instructions and have a dedicated > > storage location for an extended PSW mask and an interrupt ASCE as part > > of the interrupt call code instead. > > > > Opinions? > > Maybe I don't get it, but I personally don't quite see the advantage. It seems > to me this would make things much more complicated just to avoid a few simple > bitops. > > It maybe also depends on how many new_psws we have to touch. If it's really just > the PGM, the current solution seems simple enough. > > But if others also prefer Janosch's suggestion, I am happy to implement it.
