> > > > > > > > > > Well, it's not about the control register or MSR emulation. It is > > > > > about > > > > > the instruction decoder, which may encounter an instruction with a > > > > > memory > > > > > operand with LAM bits occupied. > > > > > > > > > OK, combine reply to you and Yuan's comments here. > > > > So you're talking about when KVM emulates an instruction, and that > > > > instruction is accessing memory, and the address for the memory can be > > > > LAM tagged. > > > > I think instruction emulation and memory access should be separated, > > > > and LAM rules should apply to memory access phase. But frankly > > > > speaking, I haven't looked into such case yet. Can you name an example > > > > of such emulated instruction? I can take a look, hoping that the > > > > emulation accessing memory falls into same code path as page fault > > > > handling. > > > > > > I do not know the usage case of LAM. According to the spec, LAM does > > > not apply to instruction fetches, so guest rip and target addresses > > > in instructions such as jump, call etc. do not need special treatment. > > > But the spec does not say if LAM can be used to MMIO addresses... > > > > The MMIO accessing in guest is also via GVA, so any emulated > > device MMIO accessing hits this case. KVM checks GVA firstly even in TDP > > Yes. And sorry, I meant the spec does not say LAM can not be used > to MMIO addresses. > BTW, it is not just about MMIO. Normal memory address can also trigger the linearize(), e.g., memory operand of io instructions, though I still have no idea if this could be one of the usage cases of LAM. B.R. Yu
