On Wed, Dec 21, 2022 at 04:49:26PM +0800, Robert Hoo wrote: > On Wed, 2022-12-21 at 16:02 +0800, Yu Zhang wrote: > > > Emm, I take a look at the callers, looks like they're segment > > > registers > > > and MSRs. Per spec (ISE 10.4): processors that support LAM continue > > > to > > > require the addresses written to control registers or MSRs be > > > legacy > > > canonical. So, like the handling on your last commented point on > > > this > > > patch, such situation needs no changes, i.e. legacy canonical still > > > applied. > > > > > > > Well, it's not about the control register or MSR emulation. It is > > about > > the instruction decoder, which may encounter an instruction with a > > memory > > operand with LAM bits occupied. > > > OK, combine reply to you and Yuan's comments here. > So you're talking about when KVM emulates an instruction, and that > instruction is accessing memory, and the address for the memory can be > LAM tagged. > I think instruction emulation and memory access should be separated, > and LAM rules should apply to memory access phase. But frankly > speaking, I haven't looked into such case yet. Can you name an example > of such emulated instruction? I can take a look, hoping that the > emulation accessing memory falls into same code path as page fault > handling. I do not know the usage case of LAM. According to the spec, LAM does not apply to instruction fetches, so guest rip and target addresses in instructions such as jump, call etc. do not need special treatment. But the spec does not say if LAM can be used to MMIO addresses... B.R. Yu
