> Emm, I take a look at the callers, looks like they're segment registers > and MSRs. Per spec (ISE 10.4): processors that support LAM continue to > require the addresses written to control registers or MSRs be legacy > canonical. So, like the handling on your last commented point on this > patch, such situation needs no changes, i.e. legacy canonical still > applied. > Well, it's not about the control register or MSR emulation. It is about the instruction decoder, which may encounter an instruction with a memory operand with LAM bits occupied. B.R. Yu
