On Wed, Apr 22, 2020 at 10:30:28AM +0200, Paolo Bonzini wrote: > On 14/04/20 02:09, Jim Mattson wrote: > > Previously, if the hrtimer for the nested VMX-preemption timer fired > > while L0 was emulating an L2 instruction with RFLAGS.TF set, the > > synthesized single-step trap would be unceremoniously dropped when > > synthesizing the "VMX-preemption timer expired" VM-exit from L2 to L1. > > > > To fix this, don't synthesize a "VMX-preemption timer expired" VM-exit > > from L2 to L1 when there is a pending debug trap, such as a > > single-step trap. > > Do you have a testcase for these bugs? Just in case you're feeling trigger happy, I'm working on a set of patches to fix this in a more generic fashion. Well, fixing this specific issue can be done in a single patch, but NMIs and interrupts technically suffer from the same bug and fixing those requires a bit of extra elbow grease. There are also (theoretical) bugs related to nested exceptions and interrupt injection that I'm trying to address. Unfortunately I don't have testcases for any of this :-(.
