On Fri, 2009-04-24 at 15:45 +0800, Zhang, Xiantao wrote: > > > As I said before, "synchronize instruction and data caches" is a > > meaningful and important operation on architectures other than IA64. > > *However*, that operation is not relevant on those architectures in > > this particular location. As far as I know, on architectures with > > non-coherent i/d caches, invalidating the icache during DMA writes > is > > unique to IA64. > > For ia64 in native system, processors depend on that platforms issue > snoop cycles to invalidate the cachable memory pages that are touched > by DMA to ensure the cache coherence from viewpoint of processors. > But for virtual machine, the DMA is emulated by memcpy in userspace, > so have to use explict instructions to emulate the snoop cycles to > invalidate icache after virtual DMAs, otherwise, processor may see old > icache and lead to disaster. That is exactly the sort of background that should have been in the commit message in the first place. Commit message aside, without comments in the code, an outside developer might very well wonder why other architectures (e.g. PowerPC) *don't* implement qemu_sync_idcache(). Are you starting to understand my objections to this patch? -- Hollis Blanchard IBM Linux Technology Center -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
