Re: [PATCH RFC 0/9] Implement handling of RH=1 for MSI delivery in KVM

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On Sat, Mar 14, 2015 at 06:00:15PM -0600, James Sullivan wrote:
> This series of patches extends the KVM interrupt delivery mechanism
> to correctly account for the MSI Redirection Hint bit. The RH bit is 
> used in logical destination mode to indicate that the delivery of the
> interrupt shall only be to the lowest priority candidate LAPIC.
> 
> Currently, there is no handling of the MSI RH bit in the KVM interrupt
> delivery mechanism. This patch implements the following logic:
> 
> * DM=0, RH=*  : Physical destination mode. Interrupt is delivered to
>                     the LAPIC with the matching APIC ID. (Subject to
>                     the usual restrictions, i.e. no broadcast dest)
> * DM=1, RH=0  : Logical destination mode without redirection. Interrupt
>                     is delivered to all LAPICs in the logical group 
>                     specified by the IRQ's destination map and delivery
>                     mode.

"When RH is 0, the interrupt is directed to the processor listed in the
Destination ID field."

> * DM=1, RH=1  : Logical destination mode with redirection. Interrupt
>                     is delivered only to the lowest priority LAPIC in the 
>                     logical group specified by the dest map and the
>                     delivery mode. Delivery semantics are otherwise
>                     specified by the delivery_mode of the IRQ, which
>                     is unchanged.
> 
> In other words, the RH bit is ignored in physical destination mode, and
> when it is set in logical destination mode causes delivery to only apply
> to the lowest priority processor in the logical group. The IA32 manual
> is in slight contradiction with itself on this matter, but this patch
> agrees with this interpretation of the RH bit:
> 
>     https://software.intel.com/en-us/forums/topic/288883
> 
> This patch has passed some rudimentary tests using an SMP QEMU guest and
> virtio sourced MSIs, but I haven't done experiments with passing through 
> PCI hardware (intend to start working on this).
> 
> Let me know your thoughts.
> 
> -James
> 
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