On 20.05.2014, at 11:59, Paul Mackerras <paulus@xxxxxxxxx> wrote:
> On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>>
>> On 17.05.14 08:20, Paul Mackerras wrote:
>>> On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
>>>> POWER8 introduces transactional memory which brings along a number of new
>>>> registers and MSR bits.
>>>>
>>>> Implementing all of those is a pretty big headache, so for now let's at least
>>>> emulate enough to make Linux's context switching code happy.
>>> [snip]
>>>
>>>> - if (!(vcpu->arch.fscr & (1ULL << fac))) {
>>>> + /* We get TM interrupts only when EBB is disabled? Sigh. */
>>> This comment doesn't make sense to me. Not every reason code reported
>>> in the high bits of FSCR corresponds directly to an enable bit in
>>> FSCR. In fact, of the 7 defined reason codes in POWER8, only three
>>> correspond to an enable bit...
>>
>> Is there any documentation on which relate to what?
>
> Yes, Power ISA v2.07 book 3S section 6.2.10 describes the FSCR enable
> bits and the interruption cause field. There are 6 cause values
> defined, of which 3 correspond to enable bits in the FSCR, and the
> other 3 correspond to things enabled/disabled in MMCR0 (usermode PMC
> anb BHRB access) or MSR (TM stuff).
I see. How's this?
Alex
commit a8e53f5f5e6c5d99363ad0d695a9ee520e1d262d
Author: Alexander Graf <agraf@xxxxxxx>
Date: Tue Apr 29 17:54:40 2014 +0200
KVM: PPC: Book3S PR: Expose TM registers
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of those is a pretty big headache, so for now let's at least
emulate enough to make Linux's context switching code happy.
Signed-off-by: Alexander Graf <agraf@xxxxxxx>
---
v1 -> v2:
- move to book3s_64 only section
- restrict to CONFIG_PPC_TRANSACTIONAL_MEM
v2 -> v3:
- check MSR.TM for TM enablement inside the guest
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index e1165ba..9bdff15 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -451,6 +451,17 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
case SPRN_EBBRR:
vcpu->arch.ebbrr = spr_val;
break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ case SPRN_TFHAR:
+ vcpu->arch.tfhar = spr_val;
+ break;
+ case SPRN_TEXASR:
+ vcpu->arch.texasr = spr_val;
+ break;
+ case SPRN_TFIAR:
+ vcpu->arch.tfiar = spr_val;
+ break;
+#endif
#endif
case SPRN_ICTC:
case SPRN_THRM1:
@@ -572,6 +583,17 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
case SPRN_EBBRR:
*spr_val = vcpu->arch.ebbrr;
break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ case SPRN_TFHAR:
+ *spr_val = vcpu->arch.tfhar;
+ break;
+ case SPRN_TEXASR:
+ *spr_val = vcpu->arch.texasr;
+ break;
+ case SPRN_TFIAR:
+ *spr_val = vcpu->arch.tfiar;
+ break;
+#endif
#endif
case SPRN_THRM1:
case SPRN_THRM2:
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 7d27a95..23367a7 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -794,9 +794,27 @@ static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac)
/* Enable facilities (TAR, EBB, DSCR) for the guest */
static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
{
+ bool guest_fac_enabled;
BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));
- if (!(vcpu->arch.fscr & (1ULL << fac))) {
+ /*
+ * Not every facility is enabled by FSCR bits, check whether the
+ * guest has this facility enabled at all.
+ */
+ switch (fac) {
+ case FSCR_TAR_LG:
+ case FSCR_EBB_LG:
+ guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac));
+ break;
+ case FSCR_TM_LG:
+ guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM;
+ break;
+ default:
+ guest_fac_enabled = false;
+ break;
+ }
+
+ if (!guest_fac_enabled) {
/* Facility not enabled by the guest */
kvmppc_trigger_fac_interrupt(vcpu, fac);
return RESUME_GUEST;--
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