On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
> POWER8 introduces transactional memory which brings along a number of new
> registers and MSR bits.
>
> Implementing all of those is a pretty big headache, so for now let's at least
> emulate enough to make Linux's context switching code happy.
[snip]
> - if (!(vcpu->arch.fscr & (1ULL << fac))) {
> + /* We get TM interrupts only when EBB is disabled? Sigh. */
This comment doesn't make sense to me. Not every reason code reported
in the high bits of FSCR corresponds directly to an enable bit in
FSCR. In fact, of the 7 defined reason codes in POWER8, only three
correspond to an enable bit...
> + if ((fac != FSCR_TM_LG) && !(vcpu->arch.fscr & (1ULL << fac))) {
so this should really check explicitly for TAR, EBB or DSCR.
Paul.
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