On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>
> On 17.05.14 08:20, Paul Mackerras wrote:
> >On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
> >>POWER8 introduces transactional memory which brings along a number of new
> >>registers and MSR bits.
> >>
> >>Implementing all of those is a pretty big headache, so for now let's at least
> >>emulate enough to make Linux's context switching code happy.
> >[snip]
> >
> >>- if (!(vcpu->arch.fscr & (1ULL << fac))) {
> >>+ /* We get TM interrupts only when EBB is disabled? Sigh. */
> >This comment doesn't make sense to me. Not every reason code reported
> >in the high bits of FSCR corresponds directly to an enable bit in
> >FSCR. In fact, of the 7 defined reason codes in POWER8, only three
> >correspond to an enable bit...
>
> Is there any documentation on which relate to what?
Yes, Power ISA v2.07 book 3S section 6.2.10 describes the FSCR enable
bits and the interruption cause field. There are 6 cause values
defined, of which 3 correspond to enable bits in the FSCR, and the
other 3 correspond to things enabled/disabled in MMCR0 (usermode PMC
anb BHRB access) or MSR (TM stuff).
Paul.
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