On 13/11/2019 12:44, Marc Zyngier wrote: > On 2019-11-13 12:50, Steven Price wrote: >> Cortex-A57/A72 have a similar errata to Cortex-A76 regarding speculation >> of the AT instruction. Since the workaround for A57/A72 doesn't require >> VHE, the restriction enforcing VHE for A76 can be removed by combining >> the workaround flag for both errata. > > Are we sure that A76 behaves the same as A57/A72 when it comes to not > caching any of the EPD* bits in the TLB? Because the 1319367 workaround > has a lot of the A72 microarch implicit to it, and I'm not sure this > works as is on A76 or A55... Hmm, well I was going purely on the errata documents which have basically the same text for all the errata. I have to admit I do not understand the microarch details here. Perhaps it would be better to leave the VHE and NVHE cases separated then? Steven > The patch itself looks OK, but I'd like some reassurance about the > above. > > M. _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
