On 13/11/2019 11:41, Steven Price wrote:
Cortex-A57/A72 have a similar errata to Cortex-A76 regarding speculation of the AT instruction. Since the workaround for A57/A72 doesn't require VHE, the restriction enforcing VHE for A76 can be removed by combining the workaround flag for both errata. So combine WORKAROUND_1165522 and WORKAROUND_1319367 into WORKAROUND_SPECULATIVE_AT. The majority of code is contained within VHE or NVHE specific functions, for the cases where the code is shared extra checks against has_vhe(). This also paves the way for adding a similar erratum for Cortex-A55. Signed-off-by: Steven Price <steven.price@xxxxxxx>
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 4f8187a4fc46..b801f8e832aa 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -744,6 +744,16 @@ static const struct midr_range erratum_1418040_list[] = { }; #endif+#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT+static const struct midr_range erratum_speculative_at_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_1165522 + /* Cortex A76 r0p0 to r2p0 */ + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), +#endif + {}, +}; +#endif + const struct arm64_cpu_capabilities arm64_errata[] = { #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE { @@ -868,12 +878,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), }, #endif -#ifdef CONFIG_ARM64_ERRATUM_1165522 +#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT { - /* Cortex-A76 r0p0 to r2p0 */ .desc = "ARM erratum 1165522", - .capability = ARM64_WORKAROUND_1165522, - ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), + .capability = ARM64_WORKAROUND_SPECULATIVE_AT, + ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), }, #endif #ifdef CONFIG_ARM64_ERRATUM_1463225 @@ -910,7 +919,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { #ifdef CONFIG_ARM64_ERRATUM_1319367 { .desc = "ARM erratum 1319367", - .capability = ARM64_WORKAROUND_1319367, + .capability = ARM64_WORKAROUND_SPECULATIVE_AT, ERRATA_MIDR_RANGE_LIST(ca57_a72), }, #endif
Have you tested this patch with both the errata CONFIGs turned on ? Having multiple entries for the same capability should trigger a WARNING at boot with init_cpu_hwcaps_indirect_list_from_array(). You could simply add the MIDRs to the midr_list and update the description to include all the Errata numbers. Suzuki _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
