On 17/08/16 11:46, Christoffer Dall wrote:
> On Wed, Aug 10, 2016 at 10:49:43AM +0100, Vladimir Murzin wrote:
>> After commit b34f2bc ("arm64: KVM: Make ICC_SRE_EL1 access return the
>> configured SRE value") we report SRE value to 64-bit guest, but 32-bit
>> one still handled as RAZ/WI what leads to funny promise we do not keep:
>>
>> "GICv3: GIC: unable to set SRE (disabled at EL2), panic ahead"
>>
>> We could keep that promise and force panic, but it doesn't look
>> reliable, instead report configured SRE value to 32-bit guest.
>
> I don't really understand this part of the commit message?
>
> Why would we force a panic, and at what time?
To make statement "panic ahead" true ;) kind of irony, so feel free to
remove that part (alternatively I can re-spin v2)
Cheers
Vladimir
>
> It is obviously correct to return the actual value that the guest should
> see...
>
> Thanks,
> -Christoffer
>
>>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@xxxxxxx>
>> Acked-by: Marc Zyngier <marc.zyngier@xxxxxxx>
>> ---
>> arch/arm64/kvm/sys_regs.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index b0b225c..0940bfc 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1360,7 +1360,7 @@ static const struct sys_reg_desc cp15_regs[] = {
>> { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
>>
>> /* ICC_SRE */
>> - { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
>> + { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
>>
>> { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
>>
>> --
>> 2.0.0
>>
>
>
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