On Tue, Aug 16, 2016 at 06:49:18PM +0100, Robin Murphy wrote: > Since the non-secure copies of banked registers lack architecturally > defined reset values, there is no actual guarantee when entering in Hyp > from secure-only firmware that the Non-Secure PL1 state will look the > way that kernel entry (in particular the decompressor stub) expects. > So far, we've been getting away with it thanks to implementation details > of ARMv7 cores and/or bootloader behaviour, but for the sake of forwards > compatibility let's try to ensure that we have a minimally sane state > before dropping down into it. > > Signed-off-by: Robin Murphy <robin.murphy@xxxxxxx> Reviewed-by: Christoffer Dall <christoffer.dall@xxxxxxxxxx> > --- > > v2: Initialise SED/ITD to safe values as well. > > arch/arm/kernel/hyp-stub.S | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S > index 0b1e4a93d67e..15d073ae5da2 100644 > --- a/arch/arm/kernel/hyp-stub.S > +++ b/arch/arm/kernel/hyp-stub.S > @@ -142,6 +142,19 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE > and r7, #0x1f @ Preserve HPMN > mcr p15, 4, r7, c1, c1, 1 @ HDCR > > + @ Make sure NS-SVC is initialised appropriately > + mrc p15, 0, r7, c1, c0, 0 @ SCTLR > + orr r7, #(1 << 5) @ CP15 barriers enabled > + bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7) > + bic r7, #(3 << 19) @ WXN and UWXN disabled > + mcr p15, 0, r7, c1, c0, 0 @ SCTLR > + > + mrc p15, 0, r7, c0, c0, 0 @ MIDR > + mcr p15, 4, r7, c0, c0, 0 @ VPIDR > + > + mrc p15, 0, r7, c0, c0, 5 @ MPIDR > + mcr p15, 4, r7, c0, c0, 5 @ VMPIDR > + > #if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER) > @ make CNTP_* and CNTPCT accessible from PL1 > mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 > -- > 2.8.1.dirty > _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
